Processes for manufacturing semiconductor devices typically include a number of photo-lithography processes and etching processes to form a pattern (s) of a circuit element (s) on a semiconductor substrate.
In general, the photo-lithography processes use a photo-mask for forming the pattern of circuits and the like using light. As the degree of integration of semiconductor devices increases, the critical dimension (CD) of the pattern formed on the photo-mask is getting smaller.
Conventionally, quartz substrates and chromium are used as materials for the photo-mask, and the photo-lithography process is used to form a pattern having a size in micrometer unit. Meanwhile, since a pattern having a size in nanometer unit may be not formed using the photo-lithography, in order to form the pattern having the size in nanometer unit, an e-beam lithography using an electron beam should be used.
However, the e-beam lithography is costly as compared with the photo-lithography, which causes cost increase.
In the prior art, Korean Registration Patent No. 10-0298175 is published on May 29, 2001.